The present invention relates generally to semiconductor memories. More particularly, the invention relates to a method and apparatus for testing semiconductor memories such as dynamic random access memories (DRAMs) and synchronous DRAMs to locate defects and/or to measure memory parameters to facilitate optimization of the memory.
In the quality control process of present day DRAMs, each memory block is tested for defects by writing patterns of data to the memory cells and then reading from the memory cells to verify that the data can be accurately stored and retrieved. In this manner, various defects within particular cells, groups of cells, word lines, sense amplifiers, and so forth, can be identified. For high density DRAMs having small feature sizes, it is also desirable to measure certain parameters such as the cell signal levels to facilitate optimization of the memory.
A DRAM cell includes a transistor and capacitor for storing a bit of data. When the transistor is activated, the capacitor is accessed for writing data to or reading data from. A plurality of memory cells are typically arranged in rows and columns to form a memory array. The rows are generally referred to as word lines and the columns are referred to as bit lines. One or more of such arrays may comprise a DRAM integrated circuit (IC) or chip.
One example of an arrangement of DRAM cells is known as a folded bit line architecture. In such an architecture, the bit lines are grouped in pairs, each pair being connected to a sense amplifier. One bit line is referred to as the bit line true and the other is referred to as the bit line bar (complementary). The sense amplifier senses and amplifies a data signal from a selected memory cell connected thereto. When a word line is selected and activated, a group of cells which are connected to the activated word line and bit lines are selected. One bit of a bit line pair is connected to the selected word line. Typically, the selected group of cells is referred to as a page. Other cell arrangements include open bit line and open-folded bit line architecture.
During normal operation, prior to reading a cell, the bit lines are pre-charged to a predetermined voltage, e.g., VDD/2, where VDD is the logic high voltage level for the memory. In a typical prior art testing approach, this pre-charge voltage Vbl is either intentionally varied and written into the cell or varied during readout. However, during a write operation, the information being written into a cell can be limited by write time and signal level. Writing Vbl into the cell can result in a different signal. Also, very high or low Vbl during readout can result in improper function of the sense amplifier.
As the density of DRAMs is continually increasing, such as from 16 Mb to 64 Mb, 256 Mb and 1 Gb, the specified time required for each memory cell to store a data bit (retention time) is increasing. To realize a higher retention time, a larger cell signal is necessary, e.g., one that results in 200-300 mV signal during sensing if no retention is applied. The sensitivity of the sense amplifier is much higherxe2x80x94it can typically sense signals down to a few millivolts. For high density DRAMs having small feature sizes, it is desirable to measure the cell signal levels, the sense amplifier sensing properties, and the contribution of isolators, bit line coupling and word line to bit line capacitance to the read out signal.
The cell signal can be estimated by taking the cell capacitance and the bit line capacitance into account. Measuring the cell signal on the actual product is difficult. This measurement requires either a special test structure to make contact to the bit lines, or a focused ion beam tool (FIB) to open contacts to bit lines. Small pads are put on the bit lines and the bit line signal is probed with picoprobes. The dense packing of the memory array renders these techniques difficult. Moreover, the physical work at the bit lines and the input capacitance of a picoprobe can influence the measurement precision. Further, substantial time is expended to apply this method to a small sample such as a few memory cells. Accordingly, there is a need for a short, relatively simple electrical test sequence to determine the cell signal by running a special test pattern.
There is also a need to obtain the distribution of the cell signal during sensing for an entire chip under different operating conditions or for different fabrication parameters. The operating point for the array, determined by the word line boost voltage (Vpp) and the sensing performance can be optimized if data is available for the cell signals of all the cells in the memory chip. Also, the process window for a given fabrication technology can be evaluated by analyzing the signals at the sense amplifiers.
The present invention relates to testing of a semiconductor memory having a plurality of memory cells arranged in rows and columns and a plurality of sense amplifiers, each for amplifying memory cell signals of a common row or column. In an illustrative embodiment, a voltage level or test pattern is written into at least one target cell of the memory cells. A word line coupled to the target cell is then activated and subsequently deactivated, to thereby modify the voltage level stored in the cell, while the associated sense amplifier is prevented from refreshing the cell as the word line is activated, e.g., by disabling the sense amplifier. A test bit line voltage is then applied to a bit line coupled to the cell to charge the bit line. Data is then read from the target cell with settings of the associated sense amplifier enabled, and compared to the original voltage level written into the cell. The process is repeated for different test bit line voltages.
The invention can be used to determine the signal at the sense amplifier associated with the target cell during normal operation of the memory, without employing complex and costly picoprobes. For example, for a single cell under test, the test bit line voltages can be varied until the output data switches logic state. The cell signal can then be derived from the test bit line voltage at the switchpoint.
The average cell signal at the sense amplifiers can be determined for the entire memory by writing a predetermined pattern into the cells, and incrementing a fail count for different test bit line voltages. The average cell signal can then be derived from the test bit line voltage corresponding to a predetermined fail count, which is a function of the number of cells in the array and the test pattern.
Advantageously, the invention can be used to determine the signals at the sense amplifiers, the bit line coupling, and the contribution of the word lines and isolators to the cell signals. The test has particular utility in the testing of high density DRAMs. Measured data obtainable with the method disclosed herein may be utilized to optimize DRAM performance with respect to the optimum voltage level for the array and the word line voltage. The test can be used to determine, for example, a weak word line, a sense amplifier mismatch, a weak cell or a bad isolator.